Implementation and validation of a hardware countermeasure against fault injection attacks

Data integrity in a processor is crucial to ensure that computations are processed without errors, preserving the consistency and reliability of the results. This is especially important in applications such as automotive, aerospace, and other critical sectors. Modern processor architectures have been shown to be vulnerable to fault injection attacks, which involve injecting errors into the circuit using simultaneous laser beams that target single or multiple data bits to compromise their integrity and extract sensitive information. This method has proven effective over the past decade through the observation of faulty behavior. Designing countermeasures against fault injection attacks has become essential to ensure data integrity, particularly with the increasing use of open-source implementations such as RISC-V, where the attacker has full knowledge of the architecture. This work proposes a fault detection methodology called "permutation-based homomorphic tags." It involves providing a redundant hardware implementation that computes arithmetic and logic operations in a permuted domain associated with a specific key. The permuted execution ensures that no faults have been injected into the processed data by preventing attackers from consistently targeting the same bits, as the permutation key is randomly changed. The outcome of this study is the hardware implementation of a permuted Arithmetic Logic Unit (ALU) and a permuted multiplier , where two different techniques were explored: an iterative approach aimed at low area consumption, and the 2-way Karatsuba algorithm for reducing latency. The architecture was implemented targeting the 64-bit RISC-V CVA6 application processor. The design was validated on Xilinx Artix-7-100T and Kintex-7 FPGAs and it was estimated the cost of the countermeasure resulted in a 7.67x area overhead and a 2.4x increase in the critical path for the ALU, a 0.31x area overhead and a 1.44x increase in the critical path for the iterative multiplier, and a 32.3x area overhead and an 8.81x increase in the critical path for the Karatsuba multiplier.