Core Concurrency in multi-core system and scheduler development for STRED architecture.

The growing demand for high computational performance and energy efficiency has made multi-core architectures a fundamental component in modern computing systems. From mobile devices to data center servers, multi-core systems allow for the execution of multiple operations simultaneously, improving speed and processing capacity without increasing the clock frequency. However, managing concurrency for resource access can present complex challenges that require innovative and optimized solutions. This thesis aims to address two main objectives in the context of multi-core and single-core architectures, with a particular focus on concurrency management and performance optimization. The first objective is the development of methodologies for managing concurrency in a specific multi-core architecture within a SER-DES (serializer-deserializer) environment. This process begins with the analysis of a specific industrial case of interest and then attempts to generalize the solutions found to improve the efficiency and robustness of concurrent operations. In this first case, the goal is to explore various synchronization algorithms and inter-core communication strategies, evaluating their robustness and criticalities. The second objective is the development of a scheduler for the STRED_L architecture (property of STMicroelectronics), a software component that, based on the type of implemented algorithm, manages the order and duration with which processes get access to the CPU, allowing for efficiency optimization and responsiveness of the system. This part will be developed for the single-core configuration, which is able to work at a frequency four times higher than the multi-core mode (quad-core). The main question we want to answer in this case is: Is a quad-core system, where up to four tasks can work in parallel, better than a single-core system with scheduling that can now run four times faster? Which of these solutions allows for higher performance, and, most importantly, how significant is the difference between them? By answering this, the ultimate aim is to make some considerations about which configuration can ultimately provide the best balance in terms of area, performance, power consumption, and cost. The developed scheduler will be tested in specific industrial scenarios and will feature a Round-Robin algorithm. The analysis will start with simple and limited solutions and will gradually become more complex, introducing features that will allow handling various cases of industrial application interest.