Fabrication and Characterization of Short-Channel Junctionless Nanowire Transistors

With the unstoppable demand for smaller, faster, and more energy-efficient electronic devices, the semiconductor industry faces a critical challenge: the continued scaling of transistor dimensions to uphold Moore's Law. Nevertheless, the downscaling limitations of conventional planar transistors require the investigation of other device structures. Because of their excellent electrostatic control and intrinsic scalability, junctionless nanowire transistors (JNT) present a feasible solution and are highly desirable for use in next-generation electronics. Due to their reduced dimensions, the Si nanowires guarantee better controllability and increased sensitivity. The key factor that characterizes the JNTs is the absence of pn-junctions. This provides several benefits, such as an easier fabrication process since the devices do not require abrupt doping profiles within the nanowire channel. In fact, the channel is now homogeneously doped. The other benefit regards the absence of complex manufacturing processes which leads to a higher scalability of the devices. The last key aspect of the short-channel JNTs is the possibility to fabricate cheaper and denser microchips since the devices provide lower power dissipation due to reduced leakages. This thesis focuses on the fabrication and characterization of short-channel Si nanowire junctionless transistors, addressing the increasing need for advanced device technologies to sustain the pace of technological advancement. Top-down approach was used to fabricate the Si nanowires, which were achieved by using e-beam lithography (EBL) and inductively coupled plasma - reactive ion etching (ICP-RIE). Through the use of nanowire architectures, which show lower short channel effects and superior gate control, this work attempts to push transistor downsizing beyond the limitations of traditional planar designs providing at the same time a CMOS compatible fabrication process. The obtained results showed the effects of the SiO2 passivation layer, which greatly improved the responsivity and controllability of the short-channel JNTs. The quality of the source and drain contacts resulted to be fundamental for a high current ratio, reaching values above 3x10^8 for the highly-doped passivated device with the channel length 50 nm. The top-gate characterizations reported the lowest hysteresis, a subthreshold swing (SS) of approximately 200 mV/dec and a drain-induced barrier lowering (DIBL) of approximately 300 mV/V. Overall, all the trends led to improved performances connected to the channel length shrinking, suggesting that the short-channel JNTs may represent indeed a valuable solution to the continuous need for scalability.