Digital Design Using Innovative Ferroelectric Spin-Orbit Coupling Devices

Over the past five decades, there has been a continuous increase in computing efficiency, driven by both transistors’s size and voltage scaling. This allowed to enhance the complexity, the parallelism of the architectures and to comply with the limited energy of edge devices. However, nowadays CMOS seems close to its technological limit because of the progressive increasing of the leakages attributed to the Boltzmann Tyranny that brought to the end of Dennard’s law. In this context, non volatile spintronic devices are promising solutions to address the challenges currently faced by CMOS technologies. Despite that, all spintronic devices currently available on the market are primarily used for memory applications. Their inability to produce an output charge current makes them unsuitable to drive the following devices for logic operations. Recent progresses in the field of spinorbitronics based on Spin-Orbit Coupling (SOC) phenomena led to novel mechanisms to perform efficient Spin-Charge Interconversion (SCI). These open to the design of a new generation of spintronic devices. In 2019, INTEL proposed an innovative MagnetoElectric Spin-Orbit (MESO) transistor which exhibits both memory and logic properties. However, the magnetoelectric control of the SCI remains a significant technological challenge. This work uses a promising alternative based on the direct ferroelectric control of the spin-orbit coupling phenomenon to build bipolar current sources. The FESO device employs ferroelectrics in order to provide both a non volatile storage of the logic state and a ferroelectric control of the output charge current direction. This results in a memory and logic device that is more compact, efficient, and faster. The main goal of this work is to design and simulate FESO based devices in order to explore the suitability of such technology for digital applications. To achieve this, a complete compact model of FESO is firstly defined and implemented in the simulation environment (CADENCE Virtuoso). Subsequently, such compact model is tested and optimized in order to guarantee both sequential and combinational propagation of the information along a chain of N identical devices. The work then focuses on exploiting the intrinsic properties of FESO, such as inversion and non volatility, for designing and testing several digital circuits. It emerges that FESO can be used to build not only memory/sequential elements like D-Latches and D-FlipFlops but also logic and complex arithmetic functions such as Majority gates, Multiplexers, Full Adders and Multipliers. The work concludes by assembling all the already validated circuits on a small 4-bit Arithmetic Logic Unit (ALU) entirely based on FESO technology. Some advantages that such devices can potentially achieve with respect to CMOS are the reduction of the chip area, the presence of the non volatility and the decrease of the static leakages. These advancements, combined with the logic and memory properties intrinsic to the FESO technology, encourage further research beyond standard Von Neumann architectures, such as in-memory computing structures and neural networks, new paradigms where the non-volatility of these ferroelectric spin-orbit coupling devices is highly advantageous.