Exploring Power Improvement Features of Advanced Physical Implementation Flow

Thanks to CPU architecture and advanced technology nodes enhancements, performance is increasing but on the other side power consumption is going higher. Due to this, the goal of this internship has been to explore and enable new and advanced power reduction techniques to ensure that the CPU architectures designed at Arm are being implemented in an optimized way, according to a given technology node. An initial investigation was carried out to find out if the Arm`s current implementation flow was correctly configured to get the best power consumption for the given CPU architectures, which was then followed by the investigation and enablement of several different EDA features and design specific optimizations whose aim was to decrease power consumption in the design, while retaining area and performance.