Design and implementation of a Time to Digital Converter on Field Programmable Gate Array

This thesis is part of a HONEY project, Progetti di Rilevante Interesse Nazionale (PRIN) in collaboration with università di Torino (UNITO) and INFN Torino, which focuses on developing innovative hybrid technology that will substantially enhance both beam monitoring and online treatment verification in Charged Particle Therapy (CPT). The first step in this project was the implementation of a high-resolution Time-to-Digital Converter (TDC) on an FPGA (Field-Programmable Gate Array), which had to meet specific technical requirements. A TDC is essential for precisely measuring the time intervals between events, which is crucial for ensuring the correct timing in the beam monitoring and verification processes. The design had to be both highly accurate and capable of operating at very high speeds to meet the stringent demands of CPT. To implement the TDC, the tapped-delay line method was selected as the preferred design approach. This method is particularly effective for time measurement as it relies on capturing the time interval between two signals: a "start" signal that marks the beginning of the interval and a "stop" signal that signifies its end. The tapped-delay line consists of a series of delay elements arranged in a chain, and each element introduces a small delay to the signal as it passes through. The moment the "stop" signal arrives, the state of the delay chain is captured using latches. These latches store the output of the delay elements at the precise moment the stop signal is received. The output of these latches is then a series of bits, where each bit corresponds to the state of a particular delay element. If a bit is high, it indicates that the signal has passed through that specific element by the time the stop signal was received. By counting the number of high bits (or "ones") after the arrival of the second signal (the stop signal), a digital representation of the time interval can be obtained. This process effectively converts the analog time difference between the two signals into a digital value. The final time interval measurement is obtained by multiplying the digital count by the resolution of the TDC. The resolution is determined by the delay of the individual delay elements in the chain. Therefore, the design’s resolution directly depends on the choice of these delay elements. Since the goal was to design the TDC on an FPGA, achieving high resolution required selecting an FPGA element that could produce the smallest possible delay. After evaluating the available options within the FPGA, the carry blocks inside the Configurable Logic Blocks (CLBs) were chosen. These blocks were selected because they generate the smallest possible delay and are easily accessible by the latches, making them ideal for implementing the delay line. The design was implemented in the Kintex Ultra scale+ FPGA. This board offers enough carry blocks in a single row and within the same clock region, allowing for a sufficient delay line. By fully utilizing the available carry blocks on the Kintex Ultra scale+, the design achieved a measurable delay of 3 nanoseconds (ns) with a resolution of 30 picoseconds (ps). This achievement, along with the ongoing testing and optimization of the TDC, positions the project to advance toward building a fully integrated hybrid system. This system is expected to significantly enhance the precision of beam monitoring and treatment verification in Charged Particle Therapy, ultimately improving cancer treatment outcomes.