The growing gap between processor and memory speeds has led to a series of prefetching techniques aimed at masking memory latency by exploiting spatial or temporal relationships in memory access patterns. However, highly efficient data retrieval techniques require a considerable amount of memory to avoid mispredictions and consequent memory loss. This internship proposal focuses on the study of a new approach to increasing the memory efficiency of our latest processor, and on the implementation of a new memory subsystem to be integrated into Arm's next-generation CPU.