polito.it
Politecnico di Torino (logo)

Generation of Local Controller code for auxiliary digital-compute in support of Compute-In-Memory (CIM)

Khalid Makroumi

Generation of Local Controller code for auxiliary digital-compute in support of Compute-In-Memory (CIM).

Rel. Carlo Ricciardi. Politecnico di Torino, Corso di laurea magistrale in Nanotechnologies For Icts (Nanotecnologie Per Le Ict), 2024

Abstract:

Compute-In-Memory (CIM) represents a cutting-edge solution for achieving high- throughput and high energy efficiency for Deep Neural Networks (DNNs) acceleration. However, AI workloads require hardware accelerators that can handle more than just dense Vector-Matrix Multiplications (for which CIM memory-tiles are uniquely well-suited). A modest, but computationally crucial, number of auxiliary operations are often required by modern DNNs. Since these operations are often not suitable for CIM memory-tiles, some sort of digital compute-cores are required, preferably implemented with extremely high energy-efficiency. To meet this requirement, the Analog AI team has designed a heteroge- neous accelerator that merges analog CIM memory-tiles with custom digital compute-cores into an “analog fabric”. In this work, the Vector Processing Unit (VPU) will be explored , a specific type of digital compute-core within this analog fabric. This VPU performs auxiliary operations as orchestrated by its Local Controller (LC). In this project, LC control-code has been generated and tested using a combination of Python, cocotb, and Xcelium. cocotb is a Python framework for performing verification of the Register-Transfer Level (RTL) used to implement the VPU, connecting between testbenches written in Python and Xcelium, an Electronic Design Automation (EDA) tool for emulating RTL. This approach allows the use of Python rather than a Hardware Description Language (HDL) such as Verilog or SystemVerilog, greatly simplifying the testbench-generation process. Such work overlaps both RTL-verification as well as preparation and tool-building for hardware accelerator testing. This project naturally connects with the workload compiler used to schedule complex DNN workloads across multiple resources, performed with an architecture simu- lator known as ADS, or Analog Deep Neural Network Simulator. In this context, cocotb emulation focuses on the LC-code for an individual resource, helping ensure that each resource processes the right data at the right time, to support the highly-pipelined DNN workflow organized by ADS.

Relatori: Carlo Ricciardi
Anno accademico: 2024/25
Tipo di pubblicazione: Elettronica
Numero di pagine: 10
Informazioni aggiuntive: Tesi secretata. Fulltext non presente
Soggetti:
Corso di laurea: Corso di laurea magistrale in Nanotechnologies For Icts (Nanotecnologie Per Le Ict)
Classe di laurea: Nuovo ordinamento > Laurea magistrale > LM-29 - INGEGNERIA ELETTRONICA
Aziende collaboratrici: IBM
URI: http://webthesis.biblio.polito.it/id/eprint/32973
Modifica (riservato agli operatori) Modifica (riservato agli operatori)