Bit-Serial Input Encoding Scheme for PCM-based Array Analog Hardware Accelerator

Analog In-Memory Computing (AIMC) for Deep Neural Networks (DNNs) enables Multiply and Accumulate (MAC) operations to be performed at the location of data, offering a promising alternative to classical von Neumann architectures. In the latter, latency and energy consumption related to the transfer of data between memory and the processing unit limit system performance. AIMC performs MAC operations energy-efficiently by utilizing an array of Phase-Change Memory (PCM) devices, where the network's weights are stored as conductances. Due to the analog nature of the computations, both digital Pulse-Width Modulation (PWM) and Analog-to-Digital Conversion (ADC) are required. PWM is used to convert the network's digital input activations into time-dependent voltage signals, while the ADC converts the result of the MAC operation—namely, the current flowing through the array of memristive devices—into a digital value. Existing PWM techniques are based on voltage-to-time conversions: the PWM receives a digital input and outputs a voltage signal with a duration proportional to the input. In this work, a novel Bit-Serial (BS) input encoding scheme will be developed to convert digital input neurons into time-dependent voltage signals. A detailed design space exploration of the accuracy-energy efficiency trade-offs of the proposed encoding scheme will be presented. Additionally, several circuit-level optimizations will be implemented in the ADC to enhance hardware performance during the conversion of the analog array's current to a digital output, aligning with the requirements dictated by the Bit-Serial encoding.