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Low-power event driven accelerator for Spiking Neural Networks on FPGA

Filippo Marostica

Low-power event driven accelerator for Spiking Neural Networks on FPGA.

Rel. Stefano Di Carlo, Alessandro Savino, Alessio Carpegna. Politecnico di Torino, Corso di laurea magistrale in Ingegneria Elettronica (Electronic Engineering), 2024

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Abstract:

Spiking Neural Networks (SNNs) represent the third generation of Artificial Neural Networks (ANNs), directly inspired by the human brain's remarkable energy efficiency. Unlike traditional ANNs, communication between neurons in SNNs occurs through discrete spikes, with information encoded in the timing of these spikes. This spike-based communication makes SNNs highly suitable for deployment on dedicated digital hardware co-processors. In the digital domain, spikes can be treated as single-bit events, active when a spike occurs and inactive otherwise. This reduces the memory footprint and interconnect resources, thanks to the small (1-bit) activations, and conserves power by updating neurons only when spikes are received. The project, EDAMAME (Event-Driven Accelerator to Model and Mimic Encephalon behavior), reflects these principles in both its name and objectives. The first phase of the project involves creating and training the SNN using Python. To achieve this, a custom event-driven neuron was developed using SnnTorch, a framework built on PyTorch for managing SNNs. A key aspect of this phase was developing a quantized model, for which the Brevitas framework from Xilinx was utilized. Brevitas is a PyTorch library specialized in quantizing neural networks. After training the SNN with various datasets and collecting the network parameters, the project moves to its second phase: implementing the SNN on a Xilinx FPGA. This phase involves verifying the SNN's functionality on the FPGA to ensure it aligns with the results from Python simulations. Additionally, a comparison is made between event-driven and clock-driven approaches, focusing on performance metrics such as latency, throughput, and power efficiency.

Relatori: Stefano Di Carlo, Alessandro Savino, Alessio Carpegna
Anno accademico: 2024/25
Tipo di pubblicazione: Elettronica
Numero di pagine: 115
Soggetti:
Corso di laurea: Corso di laurea magistrale in Ingegneria Elettronica (Electronic Engineering)
Classe di laurea: Nuovo ordinamento > Laurea magistrale > LM-29 - INGEGNERIA ELETTRONICA
Aziende collaboratrici: Politecnico di Torino
URI: http://webthesis.biblio.polito.it/id/eprint/32950
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