Spike detection circuit adaptation and optimization for ensuring safe operating testing conditions on Silicon Carbide power mosfet

This research proposes and evaluates an adaptation circuit to allow spike free testing on power discrete devices with one of the SPEA’s test cell. The objective of this device is to increase the confidence level of the manufacturers of wideband power MOSFETs on the expected lifetime of the devices tested by ensuring testing under conditions that do not wear the oxide layer significantly. The study consists of 3 consequential parts: the first one is the state of the art on the SPEA test cell to understand possible limitations due to the physical and link layers characteristics of the test cell itself. Moreover, during this part, a deep investigation on the state of the art of wideband semiconductor devices wear mechanisms is carried, with a focus on silicon carbide MOSFET devices which is the technology for which this device has started to be required in the first place. Based on the knowledge acquired during this section, a feasibility study of the detection of the high frequency spiking signals dangerous for device is carried, after defining the characteristics of these phenomena: dynamic range, time duration, type of signal to be detected (AC, DC, mixed signal) and maximal input loading effect of the device. At this stage of the research the second section of the project is carried out with a deep focus on the specific passive and IC components to be used to match the predefined requirements. The validation of the proof of concept is carried out with a SPICE based simulation accounting for some of the non-idealities of the active components and tolerances of the passive components involved. The third and last part of the project has been the prototyping and debug of the adaptation circuit to check for un-modeled characteristics of the ICs used and carrying out a more accurate performance evaluation of the architecture.