Efficient Multi-Processor Interfacing in RISC-V Systems Using Interrupt-Driven Communication and Shared Memory

This thesis investigates the interfacing of two RISC-V processors using interrupt handlers to provide efficient communication and data transfer. The study focuses on developing a method that uses interrupt-driven systems to optimize performance, particularly for IoT applications that require energy efficiency while providing relatively high performance. The thesis begins with an in-depth examination of the RISC-V architecture, including a detailed discussion of the RV32I subset, and progresses to the development of an interfacing methodology that employs shared memory and synchronization mechanisms. It then shows how a primary low-power RISC-V processor can communicate with a secondary high-power accelerator processor using interrupt signals to manage data transfer through shared memory. The provided SystemVerilog and C code demonstrate the implementation of this methodology, highlighting the roles of interrupt handlers and memory management techniques. Experimental validation was conducted entirely in a software simulation environment, employing tools such as the Xcelium Logic Simulator. Tests focused on verifying interrupt handling, data transfer accuracy, synchronization, and overall performance metrics. The experimentation, while preliminary, indicated the feasibility and efficiency of the proposed system, demonstrating the potential for reliable communication and high-performance data exchange between the processors. Key contributions of this thesis include a robust framework for multi-processor interfacing using interrupt-driven communication and shared memory, along with practical insights into memory utilization and data synchronization. The research findings suggest a lot of potential for enhancing the performance and scalability of RISC-V based systems, particularly in resource-constrained environments. Future work could extend these findings through hardware-based implementations and explore asynchronous processing techniques to further reduce power consumption and improve system responsiveness. This thesis lays a solid foundation for advancing the design and implementation of efficient multi-processor systems in various application domains.