Block floating point for FPGAs
Shancheng Li
Block floating point for FPGAs.
Rel. Luciano Lavagno. Politecnico di Torino, Corso di laurea magistrale in Ingegneria Elettronica (Electronic Engineering), 2024
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Abstract
Field-Programmable Gate Arrays (FPGAs) typically use fixed-point processors when performing floating-point operations, as this approach can effectively reduce hardware resource consumption and improve computational speed. FPGAs can also perform floating-point operations directly, but this method usually consumes more hardware resources and may reduce computational speed. Therefore, other algorithms can be used to optimize FPGA’s computation of floating-point numbers, improving computational accuracy while reducing resource consumption. Block Floating Point (BFP) has a wide range of applications in FPGA design. BFP is an algorithm used in digital signal processing. It is a method to optimize floating-point operations in computers, which can reduce memory and processor load while improving accuracy.
This paper uses the BFP algorithm to write an operation library based on the C++ language, simulating and synthesis on Vitis HLS, performing related operations on the computation, such as: initialization of integers, initialization of double-precision types, normalization, denormalization, overflow check, addition, subtraction, multiplication, division, dot product, etc
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