Block floating point for FPGAs

Field-Programmable Gate Arrays (FPGAs) typically use fixed-point processors when performing floating-point operations, as this approach can effectively reduce hardware resource consumption and improve computational speed. FPGAs can also perform floating-point operations directly, but this method usually consumes more hardware resources and may reduce computational speed. Therefore, other algorithms can be used to optimize FPGA’s computation of floating-point numbers, improving computational accuracy while reducing resource consumption. Block Floating Point (BFP) has a wide range of applications in FPGA design. BFP is an algorithm used in digital signal processing. It is a method to optimize floating-point operations in computers, which can reduce memory and processor load while improving accuracy. This paper uses the BFP algorithm to write an operation library based on the C++ language, simulating and synthesis on Vitis HLS, performing related operations on the computation, such as: initialization of integers, initialization of double-precision types, normalization, denormalization, overflow check, addition, subtraction, multiplication, division, dot product, etc. Before performing calculations, according to the theory of Block Floating Point (BFP), it is necessary to normalize the data being processed so that the data can obtain the same exponent. Before normalization, it is also necessary to calculate the headroom of each data point. After obtaining the normalized data, related operations can be performed. The key point is to judge the validity of the result, that is, to prevent possible overflow and underflow. Specifically, when performing dot product calculations, the operation library will first normalize the matrices uniformly, obtain the exponent of each individual matrix, and then perform the related matrix calculations.