Code Coverage Analysis & Enhancement of a PCIe Tile Management Block

The complexity behind modern Systems-on-Chip (SoCs) has directly impacted on the complexity of the verification process, making it increasingly challenging to achieve throughout verification and to identify and fix potential RTL issues. This led to the development of new advanced verification frameworks such as UVM (Universal Verification Methodology) and advanced features that help in detecting untested functionalities, non-executed RTL code, and non-toggling ports. To address this increasing complexity and reduce the possibility of post tape-out bugs, verification teams make use of code coverage analysis, enabling the possibility of identifying coverage gaps and develop testcases for addressing them. Throughout this thesis, we made use of the code coverage feature to gather and analyze coverage data, aiming to enhance results for a critical module within the PCIe Tile, the Tile Management Block (TMB). We introduced the PCIe architectures of the company’s first generation processor Rhea1, explained their differences, and described the verification environment employed for block-level verification. Once we provided a solid technical base behind our work and after enabling the coverage data gathering from nightly regressions, we performed a detailed RTL analysis to spot and exclude from coverage the tied-off/unconnected signals and analyzed the initial coverage results for the TMB block, identifying actual coverage gaps in the PCIe Stack Verification Plan. The main purpose behind this thesis work was to address the detected coverage gaps, focusing primarily on the addressing of the most significant gap found, which, by means of the development of a new testcase and the corresponding UVM sequences, we successfully exercised the missing functionality and covered the gap. Additionally, we listed the extra modifications performed on already existing testcases to aim for 100% code coverage. The results detailing the improvements are presented. The work performed not only improved the reliability of the verification plan of the TMB block present in the PCIe Stack subsystem, but also provided a methodology for identifying and addressing coverage gaps in future subsystems analysis.