The complexity behind modern Systems-on-Chip (SoCs) has directly impacted on the complexity of the verification process, making it increasingly challenging to achieve throughout verification and to identify and fix potential RTL issues. This led to the development of new advanced verification frameworks such as UVM (Universal Verification Methodology) and advanced features that help in detecting untested functionalities, non-executed RTL code, and non-toggling ports. To address this increasing complexity and reduce the possibility of post tape-out bugs, verification teams make use of code coverage analysis, enabling the possibility of identifying coverage gaps and develop testcases for addressing them. Throughout this thesis, we made use of the code coverage feature to gather and analyze coverage data, aiming to enhance results for a critical module within the PCIe Tile, the Tile Management Block (TMB).