Investigation on RAM access patterns for power improvements

With technology advancement in the area of transistor size, leakage consumption is becoming more and more impactful on the overall power consumption. This has prompted circuit designers to adopt low power techniques to reduce power consumption. A major concern is on cache memories, which dominate die area and are among the most power-hungry components. Some RAM memories employed in the design indeed, provide features to lower or disable temporarily the power supply, and reduce this kind of leakage consumption. During this low-leakage operating mode the memory cannot be accessed, but the data can be retained. It is important to integrate this low leakage mode without impacting too much on performances. This work aims first of all to investigate the potential power savings achieved by employing a low-power feature in cache memories, studying also the performance impact to assess its feasibility. In order to achieve to objective, a proof of concept design is firstly implemented. After collecting the results of the first design iteration, the study continues by improving the initial design based on access patterns for DATArams. The document presents, at first a brief introduction to explore the factors contribut- ing to the increase in power consumption, along with an overview of the memory structure and methods to reduce leakage in it. Subsequently, the state of the art for low power memories is presented, investigating the most used techniques to adapt a low power feature in the design. The chosen approach and its RTL implementation are described and then it follows an evaluation on the obtained result. Once assessed the feasibility of the idea further improvements on the implemented design are presented. The work is concluded with some final remarks and future works.