RTL UNR code analysis for verification closure applied to digital designs

Digital verification is an important part of integrated circuit development, ensuring that the design meets expected requirements and works correctly in all scenarios. This meticulous process involves a series of checks and tests that carefully examine the functionality, performance, and capability of the digital circuit. Through meticulous testing of the design across diverse conditions, engineers can detect and address any problems at an early stage in the development process. This approach prevents expensive revisions after production and guarantees the final product's reliability and quality. Coverage analysis is a fundamental aspect of digital verification, aimed at measuring the completeness of circuit testing. Verification engineers need to go through all uncovered parts of the design and determine the reachability of the code before excluding it. This results in a very time-consuming task. The presence of constant signals within the design influences this process. These signals, which do not change state, effectively block certain paths in the code from being reached by verification, leading to incomplete coverage metrics. These scenarios can lead to a false sense of coverage and potentially overlook critical design flaws. Overcoming this issue is essential to achieving verification closure. The objective of this thesis work is to create a tool that can analyze the RTL file and study how the constant signals propagate inside the design and affect the final coverage. This has the potential to significantly reduce the time required for manual verification by automatically excluding the parts of the circuit that don't toggle from the code coverage analysis, and it will help verification engineers to focus on the parts of the circuit that are most likely to contain errors. The tool is validated by testing it on different digital designs, applying the refine file to the results obtained from the regressions and studying how the coverage results change. It can effectively reduce the amount of uncovered signals by around 80%, substantially improving the accuracy and efficiency of digital verification efforts.