Optimizing FPGA Performance: Leveraging the Razor Technique in Digital Design

As silicon integration technology advances and clock frequencies increase, optimizing power and reaching high performances has become crucial in developing Embedded Systems and Systems on Chip (SoC). Field-Programmable Gate Arrays (FPGAs) are semiconductors that offer high flexibility as they can be reprogrammed after manufacturing, offering lower design cost and customization for specific applications. However, this flexibility comes at a price - FPGAs are less performance and energy efficient. Therefore, to achieve significant performance improvements, it is necessary to rely on architectural modifications and technology scaling of digital designs to operate beyond conventional safety limits. Typically, FPGA systems provide large timing guard bands during the design phase to guarantee safe operation across manufacturing and design. In order to achieve the demand power and performance levels, it is feasible to operate above these limits, acknowledging the possibility of errors occurring within the design and then implementing a technique for error detection and correction. This thesis aims to enhance the performance of FPGAs by implementing the Razor error detection and correction technique. The Razor technique is an innovative method that improves the performance of digital circuits, enabling faster clocking. The circuit is sampled twice using two different clocks, and any discrepancies between the two samples are detected, allowing the circuit to recover from timing errors and perform at higher clock speeds. Throughout this thesis, the intent has been to apply Razor to a Convolutional Neural Network (CNN) design for FPGAs using a custom design flow. Experimental results are obtained on the CIFAR-10 dataset using a two-layer NN on Xilinx FPGAs employing High-Level Synthesis (HLS) on both Ultra96-V2 and Kria KV260 boards. In order to implement Razor, two error recovery techniques are utilized. The first technique involves blocking the pipeline for several clock cycles to recover the error driving control signals, while the second approach uses clock gating. Regardless, it was found that applying Razor in FPGA with the proposed methods produced inconclusive results. The following chapters present a precise overview of the Razor technique and its implementation. The framework and design flow for generating NN designs are detailed, followed by an analysis of the methods and problems encountered.