Development of a slave SPMI interface module for Power Management IC

As modern electronic devices pack more features into smaller forms, the need for efficient power management becomes paramount. In this context, communication protocols like SPMI and I3C are key enablers. SPMI boasts bi-directional communication, multiple masters, and enhanced security, enabling finer control over multiple power rails and peripheral devices. I3C builds upon these benefits, adding features like error detection and correction, low-power operation, and improved addressing capabilities. Both protocols offer superior data rates and addressing mechanisms compared to I2C, making them prime candidates for efficient power management in the ever-evolving landscape of electronics. This thesis, in collaboration with ST Microelectronics, contributes to the development of an SPMI Request-Capable Slave (RCS) interface by focusing on the design and implementation of an efficient sequence transmitter operating across multiple clock domains. It addresses key challenges like metastability and clock domain crossing delays, which can lead to data errors and timing violations, through two key approaches. First, a shared asynchronous bi-directional FIFO between clock domains efficiently manages data flow, minimizing logic resources (compared to separate FIFOs) and reducing power consumption. Second, a flexible synchronization mechanism allows sending specific data directly across domains without the FIFO, further minimizing power by decreasing unnecessary toggling activity. While direct comparisons with other industrial SPMI designs are difficult, the obtained synthesis results in terms of area footprint and power consumption are promising, while timing analysis confirms the design meets all specifications. Overall, this thesis demonstrates the effectiveness of the proposed RCS design in achieving area and power efficiency, offering a valuable contribution to low-power embedded system design for industrial applications.