Development of a Workflow for Power Analysis at RTL-level Design

The objective of this thesis work is the development of a workflow for Power Analysis estimation “Front-End” that would allow an important acceleration in the design cycle by anticipating the Netlist level since, in this phase, the simulation can be extremely time consuming and, in any case, brings the designer back to the RTL stage of the project for a new Trade-off if the power specifications are not met. Specifically, is used the RTL-ARCHITECT tool developed by Synopsys. Useful to simulate circuits at the RTL level, i.e. that level of abstraction in which signals are represented as data flows between registers. The tool presents a wide range of features including the auto floorplan for a global view of the circuit layout, the extraction of metrics such as Congestion Area, Timing and Power. The purpose is the analysis of different operating scenarios of an Analog-on-top project also made up of digital IPs (Intellectual Property). The Analog IPs constituents are to be considered as analog macros modeled in SystemVerilog as well as the I/O PADs.