Modeling for Mixed-Signal Simulations

The thesis involved conducting a thorough study of some mixed-signal Application-Specific Integrated Circuits (ASIC), creating environments and workflows for their analysis and simulation, and then developing models for analog components of those ASICs. The initial stage of the thesis focused on the training required for dealing with the mixed-signal ASIC. That includes training regarding tools and techniques required for mixed-signal simulation environment setup and operation. The training also included a series of courses on advanced digital verification techniques which covered topics regarding essential SystemVerilog for design and verification, UVM, and SystemVerilog Assertions. Moreover, it included exploring best practices for modeling analog components used inside the mixed-signal ASIC in addition to understanding different modeling techniques and determining which technique to use in the simulation according to the requirements and constraints of the mixed-signal verification. The thesis started with working on the development of a configurable ramp voltage generator module that could be used in any kind of mixed-signal environment for deriving pins of other modules. This step included the development of a test bench in purely digital and mixed-signal environments to test the functionality of the ramp generator in both environments during its development. The ramp generator was modeled using different techniques which included SystemVerilog real number modeling and modeling using electrical nodes in Verilog-AMS. After testing the functionality of the ramp generator modules, they were integrated into a UVM-based test environment on a device and controlled its pins using the ramp generator. The device was simulated along with the ramp generator modules in purely digital as well as in mixed-signal environments and the results were analyzed. After the development of a ramp voltage generator, the focus was shifted to a much more complex Phase Locked Loop (PLL). The work involved a detailed analysis of the schematic and a purely analog simulation of the PLL in order to understand its design and functionality. A pre-existing faulty model for the PLL was also observed and initially, a UVM-based purely digital and a mixed-signal simulation environment was created for the PLL model in order to enable us to observe the outputs of the PLL model. The environments were created in such a way that they were coherent with the analog-only environment so that the results of each could be compared. Then by considering the analog simulation of the schematic of PLL as a reference, the faults in the PLL model were fixed and assertions were added to the model in order to ensure the correct functionality of the model. The results were verified using the assertions and a lock controller that verified the locking condition of the PLL in each kind of simulation. Then the work started on a capacitance-to-voltage converter (C2V) schematic. The main purpose was to develop a mixed-signal simulation environment for the schematic test bench of the C2V where we could replace the modules of the schematic with the models. So an environment was created where we could plug and play with models inside a schematic test bench of a C2V and run the simulation in a mixed-signal environment instead of a purely analog environment. This could help in the development of the model for the C2V making the workflow smooth and effortless.