The increasing demand for high-performance computing systems has prompted the devel- opment of advanced hardware optimization techniques to enhance the efficiency of data communication within integrated circuits. The primary objective of this research is to address the challenges associated with the design of efficient on-chip communication architectures. Traditional bus matrix designs often result in performance bottlenecks and excessive power consumption due to subop- timal routing strategies and limited bandwidth utilization. This work presents an investigation into the optimization of bus matrices to overcome above limitations leveraging hardware enhancements and to achieve significant improve- ments in both time and dynamic power consumption.