VLSI architectures optimized for the computation of floating-point transcendental functions

Nowadays the computation of trigonometric functions has great significance in various scientific areas, such as robotics, signal and image processing, 3-D graphics, and communication systems. But usually, it is performed with software routine or with the architecture of the processor using floating-point instructions. This may present long latency and slow down the program execution by spending the majority of the time in long trigonometric computation. Improvement in this can be achieved by using a dedicated unit for the calculation of trigonometric identities. Thus, this thesis aims to implement this computation with dedicated hardware to have high performances in terms of frequency, clock cycles, and instructions using the algorithm known as COordinate Rotation DIgital Computer (CORDIC). It is an iterative algorithm with which it is possible to compute trigonometric functions such as sine, cosine, hyperbolic sine, hyperbolic cosine, exponential and logarithmic functions, and multiplication and division operations. By taking initial the argument of the function as input, along with two initial values that are already established by the algorithm for each function. The algorithm computes the result in the same way, independently of the type of function selected. The operations performed in an iteration depend on the sign of the argument of the function chosen, and with each iteration, increasingly accurate values for the functions are produced and the argument is updated. The algorithm terminates in the case in which the argument reaches zero. However, it may take many iterations to reach this value, and this could be a problem depending on the task at hand. Thus an optimum number of iterations is required. For this reason, the number of iterations chosen for all the implementations developed in this thesis is 5, intended as a good compromise between the accuracy of the results and the latency needed for the computation. In this work, the binary format IEEE-754 single-precision floating-point is used for all the implementations. The initial objective consists of implementing an architecture for CORDIC that can operate at the frequency of the order of 1GHz to be compatible with modern processor cores. To reach this target, a pipeline stage has been gradually added to the starting architecture in the area identified as a critical path, generating in this way different versions of the same architecture. For each version the area, frequency, and latency have been computed, using the logic synthesis tool Synopsys Design Vision, and the simulation tool Modelsim. To enhance the latency of the iterative approach, a different version of the architecture is proposed, and it is an unrolled version of the basic CORDIC algorithm. To test the proposed design in a real scenario a RISC-V processor core is utilized. For this reason, PULPino, an open-source single-core microcontroller system from the literature, has been chosen based on 32-bit RISC-V cores. The same trigonometric functions have been computed on PULPino with and without CORDIC architecture, computing the number of clock cycles and the number of instructions in both cases. The results demonstrated that increasing the number of trigonometric functions to calculate, PULPino using CORDIC architectures takes fewer clock cycles and instructions than using its computation resources, but the cost is paid in terms of area.