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Giuseppe Intilla
Learning process to select relevant subset of parameters in CPU verification.
Rel. Andrea Bottino. Politecnico di Torino, Corso di laurea magistrale in Ingegneria Matematica, 2023
Abstract: |
Verification is a fundamental stage in the development of CPUs, ensuring their accurate and reliable functionality. It involves subjecting CPUs to a battery of tests and scenarios, simulating real-world usage to identify and rectify potential design flaws, functional discrepancies, and performance bottlenecks. In theory, the verification process should generate all possible scenarios to totally verify the CPU behaviour. In reality, the physical limitations and the limited amount of time do not allow to do that. For this reason the verification team should cleverly select some configurations to generate only representative subsets of scenario. The goal of this project is to develop an automatic process to extract a subset of relevant parameters and good configurations that impact given metrics in the verification environment. |
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Relatori: | Andrea Bottino |
Anno accademico: | 2023/24 |
Tipo di pubblicazione: | Elettronica |
Numero di pagine: | 61 |
Informazioni aggiuntive: | Tesi secretata. Fulltext non presente |
Soggetti: | |
Corso di laurea: | Corso di laurea magistrale in Ingegneria Matematica |
Classe di laurea: | Nuovo ordinamento > Laurea magistrale > LM-44 - MODELLISTICA MATEMATICO-FISICA PER L'INGEGNERIA |
Ente in cotutela: | INSTITUT NATIONAL POLYTECHNIQUE DE GRENOBLE (INPG) - ENSIMAG (FRANCIA) |
Aziende collaboratrici: | ARM France SAS |
URI: | http://webthesis.biblio.polito.it/id/eprint/28154 |
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