Spice-Level implementation and evaluation of the Logic-in-Memory paradigm

In recent years, the Logic-in-Memory (LiM) paradigm has become a widely explored topic. It is an architectural solution aimed at solving the Von Neumann bottleneck problem, which arises from the existing performance gap between CPU and memory. LiM application may be achieved by placing simple computational elements near or inside the cell of a memory array. In this way, data is locally computed inside the memory itself, leading to faster and less energy-expensive solutions. Doing so, memory arrays become larger to accomodate the additional transistors and the proper memory behavior have to be assured. This thesis explores different LiM cells (in-cell computation) which implement basic bitwise logic operations (i.e. AND, OR and XOR) between the memorized content and an external input signal. The starting point for the design of these memory cells is the 6-transistors (6T) cell, commonly employed in Static Random Access Memory (SRAM) arrays. All the used electronic elements are handled at Spice-level, through the manipulation of netlist files. To this end, taking advantage of Python language and of the OCEAN (Open Command Environment for ANalysis) language provided by Cadence, is a crucial point. Thanks to this powerful tool, it is possible to create SRAM and LiM arrays, and run simulations without the need for a graphical user interface (GUI), speeding up the whole process. The 6T cell is sized after transient analyses, which are performed to test the basic operation that are executed by a memory cell (i.e. writing, reading and data retaining). Tests are carried out exploiting some peripheral circuitry needed to carry out the operations. These circuital components are sized to properly work with the designed cells. The logic functions inside the LiM circuits belong to the Dynamic Logic family. Only the pull-down network is needed, in addition to two transistors, one for the output precharge and one footer. This logic family, compared to the Static one, reduces area occupation and delays, making it a suitable choice. The new circuits are tested in a similar way as the standard one previously mentioned. For each LiM element, the combinatorial operation must also be taken into account when performing tests to assure the proper functioning. An integrated circuit (IC) layout of the memory cell is realized to provide accurate area and performance evaluation including parasitic contributions (R and C) in the Spice models. In this way it is possible to perform simulations useful for testing the designed cells. Different layouts for the same circuit are drawn, in order to understand which configuration grants a lower parasitic contribution. Furthermore, an enhanced version of the XOR LiM cell is designed and laid out, which provides the writing of the output bit into the storage node of the successive one. Such feature is a fundamental improvement which finally allows to have the manipulated data already inside the memory array. The aim of this work is to compare the various cells in terms of area, dissipated energy and access delay, evaluating the feasibility of their implementation. As a final result, the development of memory cells which present a restrained increase in terms of energy consumption and access delay is achieved.