Vertical Junctionless Nano Transistor TCAD modeling and performance evaluation

This work presents a TCAD (Technology Computer-Aided Design) calibration procedure specifically tailored for a vertical nanowire Gate-All-Around junctionless transistor developed at the LAAS-CNRS research facility in Toulouse. The junctionless transistor is an emerging device architecture that offers potential advantages over traditional junction-based transistors in terms of process simplicity, reduced fabrication cost, and improved performance characteristics. However, accurately modeling and simulating junctionless transistors using TCAD tools require a careful calibration process due to the unique device physics and material properties involved. The proposed calibration procedure aims to optimize the TCAD model parameters to accurately represent the electrical behavior of junctionless transistors. It involves a systematic methodology that combines experimental data and simulation results to iteratively refine the model parameters. The calibration process takes into account various key factors, including the device geometry, material properties and interface effects, to ensure a comprehensive and accurate representation of the device behavior. To validate the effectiveness of the calibration procedure, a set of experimental data is used for comparison with the calibrated TCAD simulation results. The comparison involves various electrical characteristics, such as current-voltage (I-V) curves, subthreshold slope, threshold voltage, and other parameters specific to the inspected mechanisms. The calibrated TCAD models demonstrate reasonable agreement with the experimental data, indicating the accuracy and reliability of the proposed calibration procedure. In the final part of this work, the calibrated TCAD model is validated through a full TCAD simulation of an inverter. Subsequently, the inverter logic cell is used to build and simulate the behavior of a ring oscillator circuit, consisting of multiple junctionless transistors interconnected in a feedback loop. This allows to investigate the frequency response of the junctionless transistor and to get a clear view of the overall performance of the studied device. The calibrated TCAD model for junctionless transistors can serve as a valuable tool for device engineers and researchers to study and optimize the performance of novel JLNT-based architectures. It enables efficient design exploration, process optimization, and performance prediction, leading to improved device performance and enhanced manufacturing yield. Furthermore, the calibration procedure presented in this work could be extended to other emerging device architectures, facilitating their integration into mainstream semiconductor technologies.