VeriBug: Attention-based Bug Detection and Diagnosis of Hardware Designs

With ever-increasing design complexity, versatility, and ubiquity, pre-silicon hardware design verification, and bug localization has become the critical bottleneck and the most time-consuming part of the design cycle, often taking 70% of available resources. While checking behavior compliance is one side of the verification coin, the other side entails finding "what went wrong?'', in other words, the root causing the bug. Debugging functional bugs in contemporary hardware designs often takes weeks due to the hundreds of thousands of lines of design source code and several GB of simulation trace data, thereby challenging design productivity and time-to-market. To ease that pain point, in this dissertation, we propose VeriBug, a deep learning-based automated bug localization framework identifying suspicious portions in hardware design source code responsible for design failure. The principal component of VeriBug is an attention-based deep-learning architecture that tries to learn the hardware design execution semantics from its source code and execution data to behave as a parameterized hardware design simulator. VeriBug assigns a weight to each operand per operation in the source code, directly allowing it to recognize the operands that have more importance toward the design output in a failing simulation. VeriBug aggregates such weights and creates a heat map highlighting candidate design portions for further investigation. VeriBug is fully automated and adoptable in existing industrial design flows. Our initial experiments on synthetic and realistic designs show that VeriBug is highly effective and generates accurate heat-maps with low divergence (0.1 JSD on average) with respect to expected ones.