IR-Drop Aware Placement Refiner in Place and Route Design

Since the invention of Integrated Circuit during the middle ’60, the number of transistors has doubled every two years, following Moore’s Law. Nowadays, the Semiconductor Industries develop Integrated circuits (Ics) that include hundreds of millions of transistors, connected to thousands of pins through dozens of metal layers. To handle the complexity of the new technology design, specialized software are implemented to automatize this process that, otherwise, will be impossible to manage. The Integration of a large number of transistors on a very small area leads to an aggressive scaling of the technology, close to the physical limit of the atom. Therefore, in nanometer technologies, new parasitic effects are becoming relevant and they require an increasing severity in the design rules and a considerable effort from Engineers to keep them under control. In this context, this master thesis, carried out in Qualcomm Technologies, Inc (QTI) company, aims to study and improve the physical design of Ics, which a particular focus on a placement awareness technique to reduce the IR voltage drop, which is the cause of several timing issues. The IR drop phenomenon consists of a variation in the Supply voltage along the line based on the well-known formula V = RI. As a consequence, at the points where the power distribution network has a lower value, a major delay is present that could cause timing errors, or, in the worst case, functional errors. The first necessary step is to understand the whole physical design flow, from the initial floorplanning through the placement, clock tree synthesis and physical routing, moving then to final signoff checks in order to validate the design. For each step, there are many operations to perform and most of them are based on iterative algorithms aiming to find a valid solution. Therefore, different tools are used to automatize the process and it is fundamental to understand how they work singularly, which inputs require, and which outputs must produce. Moreover, all these tools are integrated into the QTI flow, which permits work at a very high level lowering the manual iteration with the tools, underlying errors, performing analysis and creating reports. Overall, the structure behind the physical design flow is complex and requires a considerable amount of time to be understood and mastered. Subsequently, the IR drop problem is analyzed and an experimental approach is followed: • To address the problem of IR drop analysis during the final signoff check, which is in a late stage of the flow, an alternative solution is studied to take care of it during the design stages. The idea is to perform early IR drop analysis and apply some precautions to mitigate the effects. •Starting from an already existing design, taken as a reference, many experiments are carried out to understand how to perform a power integrity analysis during the placement step and how to use this information to do an IR drop-aware placement. • The results are compared with the reference design, to verify the validity and benefits of the method. • Conclusions are drawn with consideration of the correlation between results and settings. The early power integrity analysis, during the implementation step, permits to be aware of the hotspots of the design before the latter is concluded, giving the possibility to perform a better placement that reduces the IR drop. Everything is handled internally during the design phase, avoiding long iteration back to the implementation stage.