IR-Drop Aware Placement Refiner in Place and Route Design
Paolo Giordano
IR-Drop Aware Placement Refiner in Place and Route Design.
Rel. Maurizio Martina. Politecnico di Torino, Corso di laurea magistrale in Ingegneria Elettronica (Electronic Engineering), 2023
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Abstract
Since the invention of Integrated Circuit during the middle ’60, the number of transistors has doubled every two years, following Moore’s Law. Nowadays, the Semiconductor Industries develop Integrated circuits (Ics) that include hundreds of millions of transistors, connected to thousands of pins through dozens of metal layers. To handle the complexity of the new technology design, specialized software are implemented to automatize this process that, otherwise, will be impossible to manage. The Integration of a large number of transistors on a very small area leads to an aggressive scaling of the technology, close to the physical limit of the atom. Therefore, in nanometer technologies, new parasitic effects are becoming relevant and they require an increasing severity in the design rules and a considerable effort from Engineers to keep them under control.
In this context, this master thesis, carried out in Qualcomm Technologies, Inc (QTI) company, aims to study and improve the physical design of Ics, which a particular focus on a placement awareness technique to reduce the IR voltage drop, which is the cause of several timing issues
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