Overcoming Limitations of Static Timing Analysis through Single-Path-Based Transistor Level Simulations in Multi-Power-Domain ASICs for MEMS Sensors

This thesis has been developed as part of an internship program with MEMS division at STMicroelectronics, with the aim to explore the available techniques to improve the accuracy of timing analysis for input/output paths of advanced MEMS sensors interfaces and validate them in any operating conditions required by the corresponding mission profiles. Typical ASICs used in these devices consist of multiple regions (power domains) characterized by a set of supply and ground nets. This allows to use different supply voltages across the design and to shut certain regions off in specific operating modes to optimize power consumption. Static Timing Analysis performed on an existing design showed violations in conditions outside the corner-case set. Because of its limits, STA was not well suited to further investigate this behavior, that is why transistor level simulations have been run instead. The dissertation deals with how to take out problematic paths and associated parasitics from device's netlist, their validation and SPICE simulations and proposes suitable solutions to various issues that may be encountered in the process. A bare-bones flow has been developed to deeply investigate all those cases where STA shows inconsistencies or lack of accuracy. The obtained results confirmed the capability of transistor level analysis in overcoming STA limitations and showed that the established set of corners for timing verification could be incomplete.