Testbench Continuous Reliability Study

The goal of this thesis is to describe the work that I have performed in 6 months of internship, explaining the treated topic, all the analysis done on it and on its possible solutions and the final implementation. The internship takes place at Arm in Sophia-Antipolis (France), where I had the luck to work from March to August. I worked on the CPU verification side, and my team was in charge of the instruction fetch unit test bench. The complexity of the modern circuits design is growing every year, to keep pace with them functional verification has to improve and increase. The current TBs are very large programs that are exposed to continuous changes; these changes can be place of undetected errors and bugs that can compromise the verification process. The aim of my internship is to implement or create a tool in order to make it able to understand if with time some features of the testbench no longer function correctly. In the first part of the internship I started to analyze all the tools available in the company, trying to understand if it was possible to implement a solution for each of them. I ran some tests for each of them to check the quality of the results. In the second part of the internship I picked the best solution and I implemented the code, tring to make it as small, fast and precise as possible. After 6 month of research I have developed a tool that is able to recognise if a feature of the testbench is disabled or not.