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Development of a high-performance Linux device driver for a custom SNN accelerator for Xilinx FPGA boards

Mauro Lanza

Development of a high-performance Linux device driver for a custom SNN accelerator for Xilinx FPGA boards.

Rel. Stefano Di Carlo, Alessandro Savino, Alessio Carpegna. Politecnico di Torino, Corso di laurea magistrale in Ingegneria Elettronica (Electronic Engineering), 2022

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Abstract:

This thesis aims to create a driver for a custom Spiking Neural Network which is able to recognize numbers from images with an IDX format. The driver will manage the gather of image information and the interface connection with the SNN. To do that the Network will be placed into the FPGA of a Xilinx ZC702 board ©.The connection will take place on an Advanced Microntroller Bus Architecture (AMBA) accessible via an AXI4 peripheral, to do such a thing a Slave interface will be created and attached on a custom VHDL block that acts as a bridge between the ARM core processor of the board and the SNN. The ultimate goal will be to boot Linux (in particular the Ubuntu 20.04LTS build) from an SD card inserted into the board, call the driver from a C application which takes the image in the IDX format and start the data exchange with the SNN on the FPGA. There will be various steps to achieve this goal: first of all an AXI4 peripheral must be chosen between the once available, for this project a full-AXI4 peripheral has been selected in order to have a 64 bits write and read bus. The AXI4-lite peripheral was also a possibility but since it only has 32 bits available and the data that the SNN receives is on 36, its usage was much more complex since 2 peripherals had to be used. The SNN, after being compiled and tested by itself, will be packed into an IP-Package of Vivado and inserted into the driver project. This is used to create the correct addresses for the board to interface the Slave port with the SNN. A schematic graph for this process is shown below and a more detailed explanation will be given in the chapter on it.

Relatori: Stefano Di Carlo, Alessandro Savino, Alessio Carpegna
Anno accademico: 2022/23
Tipo di pubblicazione: Elettronica
Numero di pagine: 63
Soggetti:
Corso di laurea: Corso di laurea magistrale in Ingegneria Elettronica (Electronic Engineering)
Classe di laurea: Nuovo ordinamento > Laurea magistrale > LM-29 - INGEGNERIA ELETTRONICA
Aziende collaboratrici: NON SPECIFICATO
URI: http://webthesis.biblio.polito.it/id/eprint/24625
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