Development and evaluation of Synthesis and Optimization strategies for digital integrated circuits.

Synthesis and optimization strategies for digital integrated circuits are topics of great importance. Interest in this area has increased in recent years because of its utility in the various fields characterized by the current technological revolution. Computer-aided design (CAD) techniques have provided the methodology for efficient and successful design of large-scale high-performance circuits for a wide range of applications, from automotive to biomedical signal processing, and so on. The exponential increase in design complexity has necessitated the development of automated techniques to achieve adequate results in shorter time. For this reason, smarter strategies need to be developed to reduce human interaction in the design process. Human interaction is time-consuming and error-prone. Strategies must overcome several challenges, from area timing, energy consumption, and testability. Testability is important to reduce testing time, which is the most expensive part of the design process. This thesis focuses on the development and evaluation of several synthesis and optimization strategies for digital integrated circuits, comparing the effects of different choices in the flow on the main design metrics, i.e., power, area and timing. The goal is to develop a flow capable of minimizing metrics with the least complexity and time. In addition, the developed strategies were verified and evaluated, showing how the key parameters affect the outcome and how the flow can be adjusted for better results. The strategies were applied in a mixed-signal ASIC design to evaluate the result. The project is starting with a basic synthesis flow that is stable and scalable, and starting from this flow, an exploration of possible further strategies is presented. The main areas in which these flow variants are developed are clock gating, the introduction of different cell libraries and the different sequences of optimizations in the flow. Clock gating was explored with the introduction of cloning techniques, or the variation of relevant parameters such as maximum fanout, minimum bandwidth and maximum number of stages. Various types of cell libraries, low leakage and low scale were used to investigate designs with less prohibitive power supply models or designs with fewer timing issues. Strategies have been developed for managing the synthesis flow, varying parameters during synthesis and thus giving the EDA tool different starting points during synthesis. The main metrics taken into account are area, power consumption and timing. Each strategy developed is consequential to the information gained from the previous strategies. The aim is to create stable alternative strategies by analysing the results obtained and the various metrics.