Highly efficient signal capture infrastructure for waveform extraction on FPGAs

With the increasing complexity of modern VLSI designs, verification is becoming one of the biggest challenges for large semiconductor companies. Since they need to get the design in the market within a reasonable timescale, and the system is too complex to cover all possible input combinations and state transitions, different verification methodologies have to be mixed in order to exploit different advantages and to cover the holes left by other methods. One of these (that is now becoming mandatory to try a huge number of input patterns in an acceptable time-to-market) is the FPGA prototyping. With this technology it is possible to achieve a throughput of two orders of magnitude higher than in simulation, with the disadvantage of a limited internal visibility. Goal of the work illustrated in this thesis is to develop a solution to enhance FPGA internal visibility, thought during a 6-months internship at Arm in the Sophia CPU Verification team. This solution is based on a chain of tools which starts its flow with a file containing a list of signals, and after the FPGA test execution, will generate a file with a dump of the selected signals during the last time window of the test. The toolchain exploits an in-house Python/C++ framework called Univent, able to manage streams of "events" in a very efficent way, and on a proprietary IP named Smart Capture as interface between Univent and the design to test.