Emulation of Aurix 3G embedded Flash read scenarios and optimization for production test coverage, throughput, and power consumption

Flash memories are non-volatile solid-state memories that can be electrically erased and programmed, based on an array of floating gate MOSFETs, thus able to retain information indefinitely, even when not powered. Thanks to good performances for read and write operations, embedded flash memories are widely adopted, especially in the System-on-Chip domain. Flash memories are characterized by a high storage density; thus, they can be affected by many possible faults, and they require complex and long test algorithms. The first part of this work is focused on the analysis of sequential read accesses performed by the CPU, called back-to-back readouts, and their timing verification. Different scenarios have been studied, fetching both data and instructions from different memory banks. In this way it was possible to compute the number of clock cycles needed to access and compare stored data with the expected one, estimating the time needed by an extensive test. The second part, instead, is about the development of low-level APIs to control a Memory Built-In Self-Test (mBIST) module, its verification, and its comparison with respect to CPU verifies. This mBIST is able to apply configurable patterns to the memory, that can be used in March-like test flows, increasing the throughput and reducing the overall test time by two orders of magnitude compared to the CPU performed test. Power consumption is estimated by the emulation system.