Verification Methodologies for Digital Design

The difficulties of System on Chip (SoC) verification and debugging have increased at the same exponential rate as Integrated Circuits (IC) hardware complexity. Over the years, design engineers developed different techniques and approaches trying to minimize verification time and reach the highest possible debug coverage. This thesis describes the System Verilog (SV) language fundamental concepts applying Object Oriented Programming (OOP) and the time limits of standard verification methodology. Universal Verification Methodology (UVM) concepts are also detailed explained to show the advantages of this approach. This methodology is based on a hierarchical testbench (TB) structure created by Accelera and gathers reusable code and less debugging time consumption on long-term projects. Additionally, both methodologies have been applied to practical case studies, where randomized stimuli have been sent to a Device Under Test (DUT) and its outputs have been compared with the expected ones predicted by TB. The test cases have proved that TB creation time for examples with standard methodology has been much longer than the one for the TBs UVM examples. Furthermore, UVM TB portability allowed to reuse each component with just minor changes rather than standard methodology where each component was re-coded for each case. In the end, an example of functional coverage code has been implemented to show how it is possible to debug specific behaviors of a DUT and measure if TB is effectively analyzing the DUT functions rather than doing only a code verification.