Early stage power estimation and power optimization on a design for laser bean scanning application

As the progress in semiconductor industry has led to the realization of increasingly complex circuits able to perform more and more operations in ever shorter times, the power consumption of these circuits is growing rapidly with their complexity, becoming a serious problem to deal with. Since an accurate power estimation requires the presence of a Clock Tree, it is usually performed at the end of the Back End process making almost impossible to modify the original design in order to reduce the power consumption. The purpose of this thesis is to find a design flow able to predict which will be the total power consumption of a circuit not at the end of the design flow but at early design stage giving the possibility to make changes to reduce power consumption as soon as possible. Then, by means of several power reduction methods, reduce the power consumed by the analyzed circuit which has been realized using a 180nm technology and used to sense the mirrors position in a Laser Beam Scanning (LBS) application. With this purpose, the power prediction features of tools, such as Design Compiler and PrimeTime-PX, have been analyzed to find the best power prediction method able to predict the power dissipated at the Post-Synthesys stage. The analysis done with the mentioned tools have been performed on a Post-Synthesis netlist using both RTL and Gate-Level switching activity. To find which method gives the best accuracy, results of each test have been compared to those obtained performing an accurate power estimation on the Post-Layout netlist. Since at the synthesis level there is no Clock Tree in the design, power prediction features of mentioned tools have been used to predict the effect of a hypothetical Clock Tree on power consumption. The first tool analyzed has been Design Compiler which allows to get a power estimation based on the switching activity given to the compiler during the synthesis process. When using a switching activity coming from an RTL simulation the error obtained was equal to the 27.1% of the total power measured for the Post-Layout netlist while the estimation performed with the Gate-Level switching activity gave an error of 14.4%. The power consumption predicted by this tool for the Clock tree has been 18.3mW for the first case and 17.2mW for the second one while the reference value obtained during the power analysis on the Back End netlist was 18.7mW. The second tool studied has been PrimeTime-PX, the same tool used to perform the Post-Layout analysis whose results have been used as reference values. Since to perform a power analysis on Gate-Level netlist using an RTL switching activity the tool requires a Map File, used to trace the name changes done during synthesis process, two different approaches have been analyzed based on how the mentioned file is generated. The first method generates the Map File just tracking the name changes of synthesis invariant elements through all the synthesis steps, while the second one uses an external SAIF file coming from an RTL simulation to populate the design name database. Error obtained with these methods are respectively equal to the 4.3% for the first case and 1.1% for the second one. As last test, an analysis on the Post-Synthesis netlist has been performed using the Gate-Level switching activity and the error obtained was equal to 0.3%. The power estimated for the Clock Tree obtained by means of the PrimeTime- PX prediction feature was 21.2mW for the SAIFLess method ...