Advanced High-performance Bus (AHB) architecture verification

Nowadays, semiconductor devices, also referred as integrated circuits and microchips are essential components in everyday electronic products. Silently they are the heroes of the technological world: they work, power, pilot, control an ever-increasing number of objects - from toys to wrist watches, from smartphones to cars and home automation products. Thanks to technological improvements such as the increasing computational capacity of chips, ever larger and faster memories, the ability to execute artificial intelligence algorithms and the reduction of their production cost, a radical change has been observed in the way we live and work. This improvement has brought challenges never faced before for companies, which have had the need to produce increasingly complex chips, while maintaining high quality standards, trying not to fall into excessive delays. If, on the one hand, we have excellent designers and increasingly advanced CAD tools, can we really be sure that what has been developed is qualitatively ready to be placed on the market? For this reason, hand-in-hand with the figure of the designer, a second one has begun to get wider and wider: the design verification engineer. In this thesis, the verification of a design and the underlying reasons were presented, applying them to a concrete example of a standard protocol for on-chip busses, developed by ARM: Advanced High-Performance Bus (AHB). Firstly, its latest revision, the fifth one, has been explained in detail, also trying to make comparisons with other on-chip protocols. Subsequently, it was worked on a verification component (VC). It can verify that an AHB design is actually consistent with the specifications. The process used is known as functional verification}, widely adopted in the semiconductor industry, with the creation of a verification plan and the extension of a partially already implemented verification environment based on a standard methodology, known as Universal Verification Methodology (UVM). The latter was presented and SystemVerilog was adopted for its implementation, as suggested by the standard itself. Afterwards, some of the attributes of the verification plan were coded and stimuli to stimulate the design were created, drawing some conclusions. The concrete intent is to connect it later to the design of a real chip and verify that the design of AHB matches the specifications. The final part of the thesis is aimed at the study of the behaviour on the bus, through the creation and analysis of a log and within some use cases. It was started by having a single master with a single slave, and then it was extended the analysis to a generic multi-master and multi-slaves architecture. Thanks to the logs, it was possible to make observations on some features such as: on which masters is given the priority, which slaves were accessed more frequently and how the wait states of the slaves can affect within a set of transfers.