Efficient LDPC implementation on FPGAs for 5G networks

Low-Density Parity-Check code, known as LDPC code, or Gallager code, has been introduced by Robert Gallager in 1963, after being forgotten for 19 years, Michael Tanner rediscovered Gallager’s paper and did research on LDPC code from the perspective of graph theory in 1981. Then in 1996, Mackay, Spielman and Wiberg found out the advantage of LDPC code in terms of its low linear decoding complexity, and its excellent performance which closes to Shannon Limit. Since then LDPC code was massively studied in research field, nowadays it became one coding standard of 5G technology. Previous work was focusing on hardware acceleration on FPGA, based on a software implementation of LDPC decoder provided by OpenairInterface Software Alliance Consortium(OAI), specifically two versions of code, Advanced Vector eXtension2(AVX2) solution and Compute Unified Device Architecture(CUDA) solution. For AVX2 version, by exploiting High Level Synthesis(HLS) tool provided by Xilinx, Hardware Description Language(HDL) was generated automatically by the tool converting from C code, the work was aborted due to the unsynthesizability of source code, then the CUDA solution was adopted, imported in OpenCL language then optimized inside the SDAceel development environment by Xilinx, finally bitstream was generated and tested on FPGA board. Th is work is continued by means of adopting the AVX2 version code and fixing the synthesizability so that it can be accepted by HLS tool. It is extremely time-consuming and error-prone converting the source code into a synthesizable version. Firstly, AVX2 instructions supported by Intel processor have to be explicitly re-expressed by means of intrinsic functions, in previous work it has been partial done and the latest version of previous work leads to massive of pointer casting problems because HLS tool doesn’t accept pointer casting among non-nature C data types. In order to solve this type of problem the data type used in the whole project has been modified, instead of having alignment of 32 bytes composed of 4x64-bits long int, it stores data in 32x8-bits, maintaining 256 bits aligned and performs calculation on 8 bits. Several more methods are performed to convert the decoder fully synthesizable. Even though the code is synthesizable it underwent an extreme long time for running a successful thesis , c onfiguration of LDPC decoder was limited to the most common used one, which is Z = 384, BG1, Code Rate = 1/3, block length = 8448. So that the synthesize time was reduced from 3 days to approximately 15 minutes. Vivado HLS 2018.2 was initially selected to perform hardware acceleration, in consequence of array partitioning not well supported, Vitis HLS 2020.2 was selected in replacement. s everal HLS methods are adopted to improve the performance, firstly data is copied from off-chip memory to on-chip memory and thus array partitioning could be adopted for accelerating calculation and data transferring. S econdly loop unrolling and pipelining are exploited alone with dependency pragmas to improve the performance. Moreover, code modification on data transferring functions is performed in order to parallelize memory reading or writing. The current optimization focuses on performance optimum because in perspective of HLS, the source code is not suitable for performing good trade-off between performance and area. T he final performance is approximately 30 times better than the previous work.