Nanosheet-GAAFETs modeling and circuit performance evaluation

During the last decade, three-dimensional electronic devices, known as Fin field-effect transistors (FinFETs), have been developed to pursue continuous technology scaling, by improving device performance while reducing short-channel effects (SCEs). However, FinFETs are currently facing many challenges in terms of performance, layout and cost for further scaling beyond the 7-nm node. As a matter of fact, nowadays, very thin and tall fin structures would be required to maintain the benefits of such a 3D device, thus raising concerns for both performance and fabrication process. In this scenario, silicon nanosheet gate-all-around field-effect transistors (NSGAAFETs) have been recognized as excellent candidates to replace fin devices for sub-7nm nodes, due to superior channel electrostatic control and greater drive current under the same footprint. The first part of this work presents the most common fabrication process for a NSGAAFET and explores its structure, made by layering one or more nanosheets which are completely surrounded by the gate. A deep knowledge of the geometry is essential to understand how to effectively model such a structure for circuit performance evaluation. The second part of the present work, instead, focuses on compact circuit models for the novel NSGAAFET devices. To this purpose, the multigate BSIM-CMG model is firstly illustrated and analyzed. Then, it is suitably modified and extended to appropriately model single- and multi-nanosheet GAAFETs. Great attention has been focused on parasitics modeling (resistances and capacitances), with the aim to derive an accurate exploration of both DC and AC performance. Furthermore, the impact of process variations has been investigated, allowing to identify the optimal values for some key parameters. Finally, the developed NSGAAFET model was successfully applied to the design and the optimization of some basic cells (inverter, NAND and NOR gates), demonstrating also its effectiveness in being used in more complex digital system design.