Design and Performance of an In-Memory Computing Architecture based on Phase-change Memory

The von-Neumann architecture, still widely used nowadays, involves a physical division between the processing and memory unit which implies a large amount of data transfer leading to issues in terms of energy and latency, known as the Memory Wall. To overcome these problems, the memory and the processing unit must be collocated in a different way, passing to a non-von-Neumann architecture. This new kind of architecture is called In-Memory Computing (IMC), in which the separation between memory and processing unit for some computations is avoided. The Computational Memory is no more seen as a passive storage element but some logic is brought inside the memory itself so that specific computational tasks can be performed locally, saving energy and time. In this thesis the computational task under analysis is the Matrix-Vector Multiplication (MVM), very used in some applications like the Compressed sensing (CS) or Deep Neural Network (DNN). The first architecture proposed to perform the MVM is based on a particular type of memristor called Phase-change Memory (PCM). Using a PCM as computational memory to perform MVM is very attractive and for this reason deeply studied in the last years. PCM is a resistance-based memory in which the information is stored in terms of conductivity: the cell could be programmed in order to stay in a Low Resistance State (LRS) if the phase-change material is in a crystalline state or vice versa it can be programmed to stay in a High Resistance State (HRS) if the phase-change layer is in an amorphous state. The binary matrix, which contains the weights, is filled with the PCM conductance values; the product between input vector and matrix is performed in an analog fashions, exploiting the Ohm’s law and Kirchhoff’s current law. The PCM main non-idealities like the Non Linearity and the Device-to-Device Variability of the conductance are studied, but also the errors introduced by the analog peripheral circuitry are taken into account. A statistical analysis of the error propagation with a certain probability density function of the input voltages is performed, and the architecture design is done looking at the system performances in terms of Resolution and Energy Consumption. The main challenge of the design is to achieve a system that exhibits a good trade-off between resolution and energy consumed. Unfortunately, analog MVM exploiting the PCM has low performances in terms of precision, due to the strong non-idealities introduced by the memristor; for this reason a competitor which performs the same MVM algorithm with a IMC architecture emulating the PCM but using a standard memory device is proposed, in order to verify if better performances could be obtained once the non-idealities of the PCM are not present anymore. To do that, the design of competitor architectures is presented and analyzed performing the same type of statistical analysis used in the PCM architecture, so that a fear comparison could be performed. In addition, a new model for the energy consumption is presented. At the end, performances comparison between all the architectures are done in terms of energy consumption with all the architectures having the same resolution and in terms of resolution with all the architectures consuming the same amount of energy.