Front-end and Architecture for In-Memory Computing based on Phase-change Memory

The spread of algorithms that process ever larger data sets is leading to a redefinition of the hardware used for computing. In particular, the implementation of these algorithms on conventional machines based on the von-Neumann architecture is inefficient due to the high costs in terms of time and energy consumed, caused by the continuous communication between the CPU and the main memory. One of the hardware innovations that is particularly promising to overcome these limitations is in-memory computing (IMC). The basic idea of IMC is to minimize the communication between the CPU and the memory to save time and energy. In order to do that, IMC involves the use of computational memories where data storage and processing happens in the same place. Since IMC is based on computational memories, emerging technologies such as resistance-based memory devices are attractive in this context thanks to their physical properties that allow to store and compute simultaneously. Resistance-based memory devices differ from standard technologies because they are able to store information in a non-volatile way through the atomic configuration of the resistive material they are made of. Among the various computational tasks in the field of in memory computing, one of the basic operations in the context of compressed sensing and deep neural networks algorithms is the matrix-vector multiplication (MVM), which could be particularly optimized with the use of resistance-based memory devices exploiting physical laws such as Ohm's and Kirchhoff's laws. The objective of this thesis is the design of an analog circuit for the implementation of MVM starting from memory cells made with phase-change memory devices (PCMs), which are ones of the most promising classes of resistance-based memory devices at the moment. Although currently PCMs are one of the most advanced technologies for in memory computing, there are still many issues that limit the performances of this type of hardware, especially in terms of precision. Since the precision of the MVM is already limited by the PCMs themselves, the non-idealities and errors introduced by the analog circuitry must be identified and controlled to obtain acceptable performances. Starting from the characterization of the PCM-based memory chip, the main non-idealities in the electrical behaviour of these devices are identified, in order to understand what level of performance can be achieved with them. The design choices of analog architecture are then discussed and their effect on the precision of the total circuit is presented, mainly through numerical simulations. At the same time, the design choices have to take into account the energy that is consumed for the MVM, to preserve one of the main purposes of IMC, which is to save energy. In conclusion, the main challenge of the entire design is the implementation of an architecture for the MVM with sufficient resolution and low power consumption. In this sense, a consumption model is presented, showing the impact of different architectural choices on energy consumption. This model is validated through circuital simulations. Finally, architectural solutions that allow to implement MVM on matrices that are not only binary but also ternary are presented and discussed. These architectures are compared with each other in order to identify which of them has the best trade-off between energy and occupied area.