Altium

Design Rule Verification Report

Date:		23/11/2019
Time:		16:09:06
Elapsed Time:		00:00:00
Filename:		C:\Users\amede\OneDrive\Documents\Tesi\ToF_TDC7200\PCB1.PcbDoc

Warnings:		0
Rule Violations:		0

Summary

Warnings	Count
Total	0

Rule Violations	Count
Clearance Constraint (Gap=10mil) (All),(All)	0
Short-Circuit Constraint (Allowed=No) (All),(All)	0
Un-Routed Net Constraint ( (All) )	0
Modified Polygon (Allow modified: No), (Allow shelved: No)	0
Width Constraint (Min=3.15mil) (Max=19.685mil) (Preferred=11.811mil) (All)	0
Power Plane Connect Rule(Relief Connect )(Expansion=20mil) (Conductor Width=10mil) (Air Gap=10mil) (Entries=4) (All)	0
Minimum Annular Ring (Minimum=3mil) (All)	0
Hole Size Constraint (Min=1mil) (Max=100mil) (All)	0
Hole To Hole Clearance (Gap=10mil) (All),(All)	0
Minimum Solder Mask Sliver (Gap=5mil) (All),(All)	0
Silk To Solder Mask (Clearance=5mil) (IsPad),(All)	0
Silk to Silk (Clearance=5mil) (All),(All)	0
Net Antennae (Tolerance=0mil) (All)	0
Matched Lengths(Delay Tolerance=10ps) (InNetClass('CLK'))	0
Height Constraint (Min=0mil) (Max=1000mil) (Prefered=500mil) (All)	0
Total	0