Proximity-based resource sharing in high level synthesis for FPGAs

Resource sharing is a well known and commonly used method employed during the design of a circuit in order to reduce its area. Usually this happens to the expense of the delay of the involved path that, if corresponding to the critical path, may affect the minimum clock period. The goal of this thesis is to prove that applying a smart resource sharing to the biggest units of the circuit, it is possible to achieve better results in terms of both area and clock period. The smart resource sharing solution that has been employed in this project relies on proximity. The algorithm is based on the belief that a cluster of units placed closer to each other should be replaced by one shared unit, while units that are located further apart should use different resources. This process leads to shorter connection wires that result into less area occupancy and, hopefully, shorter delays.